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Espressif Systems /ESP32-S3 /APB_SARADC /INT_ENA

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Interpret as INT_ENA

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (THRES1_LOW_INT_ENA)THRES1_LOW_INT_ENA 0 (THRES0_LOW_INT_ENA)THRES0_LOW_INT_ENA 0 (THRES1_HIGH_INT_ENA)THRES1_HIGH_INT_ENA 0 (THRES0_HIGH_INT_ENA)THRES0_HIGH_INT_ENA 0 (APB_SARADC2_DONE_INT_ENA)APB_SARADC2_DONE_INT_ENA 0 (APB_SARADC1_DONE_INT_ENA)APB_SARADC1_DONE_INT_ENA

Description

enable interrupt

Fields

THRES1_LOW_INT_ENA

interrupt of thres1 low
THRES0_LOW_INT_ENA

interrupt of thres0 low
THRES1_HIGH_INT_ENA

interrupt of thres1 high
THRES0_HIGH_INT_ENA

interrupt of thres0 high
APB_SARADC2_DONE_INT_ENA

interrupt of sar2 done
APB_SARADC1_DONE_INT_ENA

interrupt of sar1 done

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data